1. Field of the Invention
The present invention relates to a method of analyzing electromagnetic interference (EMI), and more particularly, to a method of analyzing electromagnetic interference arising in a large-scale, high-speed LSI (large-scale integrated circuit) by means of high-speed, highly-accurate logic simulation.
2. Desaription of the Related Art
As is often the case, in the field of computers, LSIs find a broadening range of applications, from communications devices, such as cellular phones, to general household products, toys, and automobiles. Electromagnetic interference arising in such a product induces radio interference noise to arise in a receiver, such as a TV set or a radio, or faulty operations of another system. In order to prevent this problem, the entirety of a product is shielded, or filters are provided in a product. With a view towards preventing an increase in the number of components and cost and difficulty in preventing occurrence of electromagnetic interference in a product, strong demand exists for suppression of noise in an LSI alone.
Under such a situation, an LSI is ranked as a key device for any product which contains an LSI. Demand exists for an larger-scale, high-speed LSI for ensuring competitiveness of a product. In a situation in which the cycle of product development becomes shorter, design-automation of an LSI is indispensable for satisfying the demand. There is growing necessity for adopting synchronous circuit as a condition for introducing a state-of-the-art design-automation method. In a case where all circuits of a large-scale, high-speed LSI operate synchronously with a reference clock signal, instantaneously-changing current becomes very large, which induces an increase in electromagnetic interference.
The present invention relates to a simulation method which enables evaluation of EMI indispensable for reducing electromagnetic interference while maintaining a tendency toward a larger-scale, higher-speed LSI.
Noise imposed on another device by an LSI is roughly classified into two types; radiation noise, and conduction noise. Radiation noise emanated directly from an LSI includes noise emitted from internal wires of an LSI. However, internal wires do not act as an antenna of large size. As a matter of course, it is considered that the noise emitted directly from an LSI will pose a problem in the future, in association with an improvement in the operation frequency of an LSI. However, as of now, the noise emitted from the inside of an LSI is considered trivial.
In contrast, conduction noise affects another device mounted on a printed board by way of direct interconnections, such as internal wires of an LSI, lead frames, or wiring patterns provided on a printed wiring board. Noise is emitted from such interconnections while the interconnections are taken as the source of origination or as an antenna. The antenna constituted of the interconnections is much larger than that constituted by internal wires of an LSI and is a dominant element in terms of electromagnetic emission.
A power line and a signal line can act as paths along which conduction noise developing in an LSI travels. In consideration of an electromagnetic field in the vicinity of an LSI, noise which results from variation in an electric current of a power source being emitted from a power line serving as an antenna is considered to be dominant. There may be a case where a ringing overshoot stemming from variation in a signal poses a problem. However, there more frequently arises a case where variation in an internal power level of an LSI propagates as a signal waveform, to thereby present a problem. Noise emitted from a power line or a signal line is considered to have a strong correlation with variation in the electric current of a power source (hereinafter referred to as a “source current”).
A source current of a CMOS circuit will now be described by reference to a simple inverter circuit. In a case where variation arises in a voltage applied to an inverter circuit, there flows a load capacitance charge/discharge current, which is the primary source current of the CMOS circuit. In addition, a short circuit current flows together with the load capacitance charge/discharge current. In design of such a CMOS circuit, all circuits of an LSI are synchronized in accordance with constraints on the use of a design-automation tool. As a result of all circuits being synchronized, all circuits of the LSI operate simultaneously, and a peak current arises in a power source in synchronism with a reference clock signal. Further, in order to increase operating speed, or shorten a cycle, of the LSI, the capacitance of a transistor is increased so as to enable a charging/discharging operation to be completed within a short period of time. Eventually, a peak current increases. As a matter of course, the total source current of an LSI is increased even when the scale of an LSI is increased. Thus, the peak current of the power source is increased, thereby inducing occurrence of an abrupt change in a source current. Such an abrupt change induces an increase in higher harmonic components, thereby resulting in an increase in electromagnetic interference.
Highly-precise simulation of change in a source current, which may be said to primarily account for electromagnetic interference, is considered to be effective in evaluation of electromagnetic interference arising in an LSI.
A current simulation method for effecting transistor-level current analysis, as will be described below, has conventionally been employed.
FIG. 116 is a block diagram showing the flow of processing operations pertaining to a conventional EMI analysis method. According to this method, on the basis of layout information pertaining to an LSI to be analyzed through use of a method of analyzing an electric current of a transistor, there is performed processing pertaining to a layout parameter extraction (hereinafter referred to simply as an “LPE”) step O3. Subsequently, there is performed processing pertaining to a circuit simulation step O6 for effecting simulation of a circuit on the basis of a switch-level netlist; a source-of-current modeling step O8; a source line LPE step O10; a transient analysis simulation step O12; and a FFT step O14.
Processing pertaining to each of the foregoing processing steps will now be described by reference to FIG. 116.
First, there are input data O1 pertaining to the layout of a semiconductor integrated circuit (hereinafter referred to simply as “layout data O1”), which circuit is to be subjected to EMI analysis; parameters of elements, such as transistor elements or various parasitic wiring elements (e.g., resistors and capacitors); and an LPE rule O2 for defining a form in which extracted layout parameters are to be output. In step O3, parameters of the respective elements included in the layout data O1 are calculated in accordance with the LPE rule O2, to thereby prepare a netlist O4. In step O3, parameters of parasitic elements of a power source (and the ground) are not extracted.
In step O6 are input the netlist O4 prepared in step O3 and a test pattern O5 for replicating a desired logic operation in a circuit serving as an object of analysis. There are calculated a load capacitance charge/discharge current and a short circuit current, both responding to the operating state of an internal circuit, wherewith information O7 about the waveform of an electric current of each transistor (hereinafter referred to simply as “current waveform information O7”) is produced. The first operation of the processing pertaining to step O6 is effected on the assumption that the potential of a power source (and that of ground) is a variation-free, ideal potential.
In step O8, the current waveform information pieces O7 concerning the respective transistors prepared in step O6 are entered. Each of the thus-entered current waveform information O7 pieces is modeled into a mode which can be applied to subsequent step O12, wherewith information O9 concerning a source-of-current element model (hereinafter referred to simply as “source-of-current element model information O9”) is prepared. According to a common method, in order to alleviate the load associated with processing pertaining to step O12 and subsequent steps, each functional circuit block consisting of a plurality of transistors is modeled as a source-of-current element.
Processing pertaining to step O10 differs from processing pertaining to step O3, only in that parameters of parasitic elements of a power source and parameters of those of parasitic elements of ground wiring (e.g., resistors, decoupling capacitance, and like elements) are extracted and subjected to EMI analysis in lieu of extracted parameters of transistor elements and extracted parameters of various parasitic wiring elements. Hence, repeated explanation of processing pertaining to step O10 is omitted. In step O10, a power source (and ground) wiring netlist O11 is prepared.
In step O12, there are entered the source-of-current element model information O9 prepared in step O8, the power source (and ground) wiring netlist O11 prepared in step O10, and an impedance O16 (including, resistance, capacitance, and inductance) of a wire or lead frame. Through analysis of these input data carried out by a transient analysis simulator typified by SPICE, variation in the line voltage of a circuit to be analyzed is calculated, wherewith a line voltage drop result O17 is prepared.
Subsequently, processing pertaining to step O6 is performed again. In contrast with the first operation of the processing pertaining to step O6 having been effected on the assumption that the potential of the power source (and the ground) is a variation-free, ideal potential, the line voltage drop result O16 prepared in step O12 is entered, and the current waveform information pieces O7 concerning the respective transistors are prepared again in consideration of the line voltage drop. Similarly, processing pertaining to steps O8 and O12 is performed again.
Processing pertaining to steps O6, O8, and O12 is effected several times in a looped manner, wherewith there is produced a current waveform result O13 which duplicates variation in a line voltage with high precision.
In step O14, the current waveform result O13 prepared in step O12 is entered and subjected to fast Fourier transformation (hereinafter abbreviated FFT), to thereby enable frequency spectrum analysis. There is obtained an EMI analysis result O15.
In the conventional example, the precision of verification varies greatly according to combination of processing pertaining to the LPE step O3, processing pertaining to the source line LPE step O10, and processing pertaining to the source-of-current modeling step O8. However, a certain level of accuracy of analysis can be expected. A transient analysis simulator typified by SPICE is used for transistor-level analysis of an electric current. Hence, a limitation is imposed on the level of a circuit to be analyzed, and an enormous amount of processing time is required. The level of a semiconductor integrated circuit has increased recently, and establishment of an EMI analysis method which enables high-speed analysis of an electric current on a larger scale than a transistor level by dealing with the analysis in abstract more than a transistor level dealing is desired.
A gate-level current analysis method (hereinafter referred to as a “gate-level power consumption analysis method”) has conventionally been proposed as a current analysis method which can be made faster. This gate-level current analysis method is used for analyzing power consumption.
The gate-level power consumption analysis method for estimating power consumption on a gate level comprises the following steps: namely, a step of preparing beforehand a library from the total amount of electric current required per change when a logic signal appearing at an output port of a circuit element is changed from a logic value of 0 to 1 or from a logic value of 1 to 0; and a step of adding, to a total amount of current of the entire circuit at each time, a total amount of electric current required per change when a logic signal appearing at an output port of an instance in a circuit, the circuit being an object of estimation of power consumption, is changed from a logic value of 0 to 1 or a logic value of 1 to 0, to thereby estimate the total power consumed by the overall circuit (i.e., a value obtained by means of multiplying the total amount of current by an external voltage). FIG. 109 shows the configuration of an example system for effecting the conventional, popular gate-level power consumption analysis method. The gate-level power consumption analysis system shown in the drawing is operated through use of an amount-of-current analyzer comprising circuit connection information storage means 1001; signal pattern storage means 1002; means 1003 for storing the amount of electric current flowing through an element (hereinafter referred to simply as “element current storage means 1003”); total-amount-of-current storage means 1004; and total-amount-of-current calculation means 1005.
Individual elements constituting the gate-level current analysis system shown in FIG. 109 will now be described. Procedures for calculating the amount of current shown in FIG. 113 will be described, by reference to the gate-level circuit connection information shown in FIG. 110, a pattern of signal change arising at each terminal shown in FIG. 111, and the amount of current flowing through respective elements shown in FIG. 112.
The circuit connection information storage means 1001 stores circuit connection information concerning connection of circuits which are objects of analysis. Circuit connection information, such as that shown in FIG. 110, is stored in the circuit connection information storage means 1001 in advance. The circuit connection information is generally called a netlist.
The circuit connection information comprises an external input port D, an external clock signal input port CLK, an external output port Q, flip-flops FF1 and FF2, a buffer element BUF1, and wires D1 and Q1 for interconnecting elements. Each of the flip-flops FF1 and FF2 comprises a data input pin D, a clock signal input pin CK, and a data output pin Q. A logic value appearing at the data input pin D immediately before arrival of a leading edge of a clock signal input to the clock input pin CK is transmitted to the data output pin Q.
The buffer element BUF1 has a data input pin A and a data output pin Y. A logic value appearing at the data input pin A is output to the data output pin Y.
The above elements have a lag, such as an intra-element lag, and permit propagation of a signal with a time lag of 1 ns. The external input port D is connected directly to the input pin D of the flip-flop FF1. The external clock input port CLK is a terminal for receiving variation in a clock signal from the outside and is connected directly to the input pin CK of the flip-flop FF1 and to the input pin CK of the flip-flop FF2. The external output port Q is connected directly to the output pin Q of the flip-flop FF2 and outputs a signal value of the flip-flop FF2. A wire D1 interconnects the output pin Y of the buffer BUF1 and the input pin D of the flip-flop FF2. A wire Q1 interconnects the output pin Q of the flip-flop FF1 and the input pin A of the buffer BUF1.
The signal pattern storage means 1002 stores a pattern of signal change applied to information concerning connections of a circuit to be analyzed. As shown in FIG. 111, a pattern of change in a signal input to the input port CLK and a pattern of change in a signal input to the input port D shown in FIG. 110 are stored in the signal pattern storage means 1002 in advance. The horizontal axis in FIG. 111 represents the time at which change arises in a signal pattern. Upon each change, the signal pattern is changed between a logic value of 0 and a logic value of 1.
The element current storage means 1003 stores information concerning the amount of electric current flowing through an element; that is, information concerning the total amount of electric current flowing when single change arises in an external terminal of each element. Information concerning the amount of electric current flowing through an element, such as that shown in FIG. 112, is stored beforehand in the element current storage means 1003. Reference numeral 1301 designates the amount of electric current flowing through a flip-flop FF when change arises in a signal input to the clock signal input terminal CK of the flip-flop FF. Reference numeral 1302 designates the amount of electric current flowing through the flip-flop FF when change arises in a signal output from the output terminal of the flip-flop FF. Reference numeral 1303 designates the amount of electric current flowing through the buffer BUF when change arises in a signal output from the output terminal Y of the buffer BUF.
The total-amount-of-current calculation means 1005 is given a flowchart such as that shown in FIG. 114.
In step 1501, the circuit connection information which is stored in the circuit connection information storage means 1001 and is shown in FIG. 110 is read. In step 1502, a signal pattern stored in the signal pattern storage means 1002 and shown in FIG. 111 is read. In step 1503, information concerning the amount of electric current (hereinafter referred to simply as “element current information”) stored in the element current storage means 1003 and shown in FIG. 112 is read.
In step 1504, the signal pattern shown in FIG. 111 is delivered to the circuit connection information shown in FIG. 110, to thereby enable propagation of a signal. When change arises in a signal appearing at the external terminal of a circuit element written in the element current information, the amount of electric current flowing through the external terminal is added to the information concerning the total amount of electric current at each time. A signal propagation method used herein is identical with a signal propagation method employed in a timing simulator. More specifically, the method is to calculate, in time sequence, change arising in a real circuit in accordance with a given signal pattern by means of tracking circuits which are affected by the signal pattern. The signal propagation method employed in a timing simulator is generally embodied in the form of a plurality of commercial tools. Hence, detailed description of the signal propagation method is omitted. FIG. 112 shows change in a logic value of a signal appearing at each pin, which has been caused as a result of propagation of the signal pattern in each step.
FIG. 112 shows change in a logic value in the same form as that in which the signal pattern is shown in FIG. 111. After completion of propagation of the signal, in step 1505 the information concerning the total mount of electric current calculated at respective times shown in FIG. 113 is stored in the total-amount-of-current storage means 1004. The total-amount-of-current storage means 1004 stores the information concerning the total amount of electric current detected at respective times according to the foregoing procedures, in the form shown in FIG. 113.
In a case where information concerning the total amount of electric current is calculated in greater detail, a load dependence coefficient of a current which is dependent on an output load capacitance (or on a charge current) and the total amount of electric current which is not dependent on an output load capacitance (or on a short circuit current) are stored in an element current storage section. Thereafter, information concerning the capacitance of each wiring (i.e., capacitance information) is read, the sum of the load-independent current and the product of the capacitance information and the load dependence coefficient is taken as the total amount of electric current. As described above, according to the conventional gate-level power consumption calculation method shown in FIG. 110, the amount of electric current flowing upon a single change arising in a signal appearing at an input or output pin is taken as a unit or as flowing momentarily. In other words, the conventional method determines only the total amount of electric current. In terms of power consumption, the accuracy of the thus-calculated total amount of current is sufficient. However, EMI analysis requires information concerning chronological change in electric current, and the total amount of electric current is not sufficient in terms of EMI analysis.
The conventional example using the transistor-level current analysis method can be expected to yield a certain level of accuracy. However, a transient analysis simulator typified by SPICE is used for transistor-level current analysis. A limitation is imposed on the level of a circuit to be analyzed, and an enormous amount of processing time is required. The scale of a semiconductor integrated circuit has increased recently, and establishment of an EMI analysis method which enables high-speed analysis of an electric current at a larger level than a transistor level is desired.
In the conventional example using the gate-level current analysis method, high-speed analyses of a current is feasible. However, only the total amount of electric current is determined. The gate-level current analysis method is sufficient in terms of power consumption but in insufficient in terms of EMI analysis.